曙海教育集团
上海:021-51875830 北京:010-51292078
西安:029-86699670 南京:4008699035
成都:4008699035 武汉:027-50767718
广州:4008699035 深圳:4008699035
沈阳:024-31298103 石家庄:4008699035☆
全国统一报名免费电话:4008699035 微信:shuhaipeixun或15921673576 QQ:1299983702
首页 课程表 报名 在线聊 讲师 品牌 QQ聊 活动 就业
嵌入式OS--4G手机操作系统
嵌入式硬件设计
Altium Designer Layout高速硬件设计
开发语言/数据库/软硬件测试
芯片设计/大规模集成电路VLSI
其他类
 
   Low Power Implementation(Cadence)培训
   班级规模及环境--热线:4008699035 手机:15921673576( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
Low Power Implementation(Cadence):即将开课,详情请咨询客服!
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

  Low Power Implementation(Cadence)培训

培训方式以讲课和实验穿插进行。

Cadence? Incisive? Enterprise Simulato主要利用系统级至门级的涵蓋率來驱动功能验证和除错分析进一步促进的验证的效率及可预测性。Cadence Incisive Enterprise Simulator?提供testbench制作、共用和分析能力,可从系统级至RTL再到门级验证其设计,利用此环境从计划至完成皆可支援涵蓋范围驱动的运算法,而其原位编译的模组可在传统同步模拟加速並同时模拟关于behaviortransation(TLM)?RTL和门级模型,以达到有效改善同步模拟的不良性能。它也支援工业标准的验证语言並且与开放验证运算法相容(OVM),因此工程师能迅速简单地整合Cadence Incisive Enterprise Simulator以建立所需要的验证流程。

COURSE OUTLINE

MDV (Metric Driven Verification) foundations workshop

·?????????MDV Foundations introduction

–??MDV Foundations Planning

–??Introduction to Planning

·?????????Verification Plan Development

–??Lab 1: Launching Your First Regression

–??Lab 2: Review the Default vPlan View in Enterprise Manager

–??Lab 3: Creating Reusable Verification Plans

–??Lab 4: Creating a Top Level Verification Plan

–??Lab 5: Detecting Changes in the New Specification

–??Lab 6: Review the vPlan in vManager

·?????????MDV Foundations Infrastructure ?

–??Lab 1: Your First Enterprise Manager Regression

–??Lab 2: Integrating project build and run

·?????????MDV Foundations Management

–??Lab 1: Create your own first failures view

–??Lab 2: Rerun Failures

–??Lab 3: vPlan Analysis

–??Lab 4 : Report generation

?

Low Power Verification Workshop

???????????Introduction

–????????Introduction to Low Power Terminology

–????????CPF Creation

–????????Lab: Understanding the power information from a CPF file - Solution

???????????Low Power Simulation Verification

–????????Verification Planning and Metrics for Low Power

–????????Low-Power Simulation

–????????TCL Commands for Debug

–????????Debugging with SimVision

–????????Automatic Assertions

–????????Lab: Low-Power Simulation Debug




Assura Verification


The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.


Learning Objectives
In this course you will:
? o Verify your physical IC design with Assura Verification?
? o Set up and run DRC and LVS?
? o?Locate and display results from DRC and LVS runs?
? o Run verification in various input and run modes


Audience
? o CAD Developers
? o Design Engineers
? o? Layout Designers


Prerequisites
? o Layout design experience
? o Physical verification experience
? o UNIX OS


Course Agenda

Unit 1

? o?Introduction?
? o?Using Assura Verification?
? o?Operational details?
? o?Inputs and outputs?
? o?Interactive debugging environment?
? o?DRC and LVS runs
? o?Running design-rule checks (DRC)?
? o?DRC error debugging techniques?
? o?Error Layer Window?
? o?Setting up DRC run parameters

Unit 2

? o?Running design rule checks (continued)?
? o?Antenna check?
? o?Density check
? o?Running layout versus schematic (LVS) checks?
? o?Understanding and debugging LVS check reports?
? o?Setting up LVS run parameters?
? o?Displaying errors using the graphical user interface?
? o Locating LVS errors

Unit 3

? o Running layout versus schematic checks (continued)?
? o?Debugging LVS with multiple errors?
? o?Using the main debugging tools?
? o?Mismatched nets and mismatched devices?
? o?Shorts locator and opens locator?
? o?Malformed devices?
? o?Pins, parameters, and rewire tools
? o?Unguided debugger lab module?
? o?Running an electrical rules check (ERC)